1. Field of the Invention
The present invention relates generally to the field of integrated circuit fabrication and, more particularly, to a buried digitline (BDL) access device with a metal shield between digitlines, and a memory array using such BDL access device.
2. Description of the Prior Art
A continuous challenge in the semiconductor memory industry is to decrease the size of memory cell components in order to increase the packing density of the DRAM chip. Over the last few device generations, DRAM manufacturers have developed alternative cell layouts that reduce the area they occupy on the chip. The latest designs allow a significant increase in density by burying the address lines or digit lines in the silicon substrate, then fabricating the transistor and capacitor on top to form a vertical stack. Such devices are also known as buried digitline (BDL) access devices.
However, the current BDL technology still has several drawbacks. For example, the BDL access device has high digitline-to-digitline (DL-DL) coupling capacitance as a percentage of the total digitline capacitance. The higher percentage of DL-DL coupling causes significant sense margin loss even though the total digitline capacitance may be lower than other technologies. Hence, it is desired to provide an improved BDL device for DRAM applications, which are capable of reducing the percentage of DL-DL coupling compared with the total DL capacitance.